In current semiconductor industry, integrated circuit (IC) products can be divided into three categories, i.e., analog circuits, digital circuits and digital/analog hybrid circuits. Memory device is an important type among digital circuits. In recent years, among memory devices, the development of flash memory is particularly rapid. A main feature of flash memory is the ability of long-term information storage without electric power. Therefore, flash memory have been widely applied to memory devices that need to retain stored data without losing the data due to a power outage and need to repeatedly read and write data. In addition, flash memory has a number of advantages such as high degree of integration, fast access speed, and ease of erasing and rewriting. Thus, flash memory devices are widely applied in many areas such as microcomputers, and automated control. Accordingly, how to improve performance of flash memory and reduce cost has become an important issue.
Furthermore, developing high-density flash memory technology can help to improve the performance of various types of portable electronic devices. For example, flash memory is used as a storage device in electronic devices such as digital camera, laptop, or tablet computer. Therefore, reducing the size of a flash memory cell and thus reducing the cost of the flash memory cell is one of the directions of technological development. For NOR gate electrically erasable programmable read-only memory with tunnel oxide layer (i.e., EPROM with Tunnel Oxide, ETOX, or Erase Through Oxide) flash memory, using a self-aligned electrical contact (i.e., Self-Align Contact) technology can reduce the size of the flash memory cell.
FIG. 1 depicts a cross-sectional view of a flash memory device formed using a self-aligned electrical contact process. The flash memory device includes a substrate 100 and one or more adjacent memory cells 101 on the surface of the substrate 100. One memory cell 101 includes a tunnel oxide layer 110 on the surface of the substrate 100, a floating gate layer 111 on the surface of the tunneling oxide layer 110, an insulating layer 112 on the surface of the floating gate layer 111, a control gate layer 113 on the surface of the insulating layer 112, and a silicon nitride layer 114 on the surface of the control gate layer 113.
In addition, the flash memory device includes a source region or a drain region 102 within the substrate 100 between adjacent memory cells 101. The flash memory device further includes sidewall spacers 103 on the surface of the substrate 100 on both sides of the memory cells 101. The flash memory device further includes an electrical interconnect structure 105 on the surface substrate of the sidewall spacers 103, on the surface of the silicon nitride layer 114, and on the surface of the substrate 100 between the adjacent memory cells 101.
In order to reduce the resistance of the control gate layer 113, and accordingly to improve performance and stability of the flash memory device and reduce energy consumption and heat loss, a metal silicide layer 115 is formed in the control gate layer 113 using a self-aligned silicide process. In addition, the metal silicide layer 115 is located on a portion of the sidewall surface of the gate control layer 113.
However, the flash memory device formed using existing technology still has relatively low stability and poor reliability. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.